Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Hfo2 Gate Breakdown And Channel Hot Electron Effect On Mosfet Third-Order Intermodulation

The effect of n-channel hot electron and p-channel gate oxide breakdown (BD) on the third-order intermodulation of HfO2 MOS transistors has been studied. Both reliability physics mechanisms result in a similar shift of the intermodulation intercept point characteristics versus the absolute value of gate-source voltage. However, the device VIP3 in the subthreshold region is sensitive to BD leakage current and BD location effect. The third-order input intercept point as function of stress time was evaluated experimentally and compared with the analytical model predictions. A good agreement between the model predictions and experimental data is obtained. © 2008 IEEE

Rf Reliability Subject To Dynamic Voltage Stress In Nmos Circuits

NMOS transistor degradation due to dynamic stress was examined experimentally. The degradation in radio frequency performance, such as linearity and noise figure, are evaluated. A power amplifier is used as a circuit example to demonstrate the effect of dynamic stress on RF circuit performance. ©2005 IEEE

Mos Rf Reliability Subject To Dynamic Voltage Stress - Modeling And Analysis

Dynamic stress on MOSFETs with 900-MHz inverter-like waveforms as well as static (or dc) stress were evaluated experimentally. It showed that the degradation due to dynamic stress is less than that of dc stress for our test transistors. A compact model is used to evaluate the degradation in radio frequency performances, such as transconductance, cutoff frequency, linearity, and noise figure. A class-AB power amplifier is presented as an example to demonstrate the effect of dynamic stress on RF circuit performance. © 2005 IEEE

Hot Carrier-Induced Degradation On High-K Trnasistors And Low Noise Amplifier

Channel hot carrier-induced DC and RF performance degradations in 60 nm high-k nMOSFETs are examined experimentally. The normalized degradation in RF parameters can be predicted using normalized transistor parameters. Good agreement between the analytical predictions and simulation results is obtained. ©2006 IEEE

Cmos Device And Circuit Degradations Subject To Hfo2 Gate Breakdown And Transient Charge-Trapping Effect

The gate leakage current of HfO2 MOSFETs exhibits the power law characteristics after soft breakdown (BD) and the linear behavior after hard BD. Fast transient charge-trapping effect (FTCTE) shifts the inverter transfer characteristics but does not affect the high and low output voltages. The ring oscillator remains functional after gate BD. The BD position near the drain end of the n-channel transistor increases the noise figure (NF) significantly, whereas FTCTE has minor impact on the NF of the folded cascode low-noise amplifier. © 2007 IEEE

Electrical And Temperature Stress Effects On Class-Ab Power Amplifier Performances

Normalized degradations of drain efficiency and output power as a function of conduction angle, maximum drain current, and maximum output voltage are modeled. Good agreement between the model predictions and Cadence radio-frequency simulation results is obtained. The output power and efficiency of class-AB power amplifiers (PAs) degrade with channel hot electron stress due to reduced conduction angle, drain current, and output voltage. The degradation is enhanced at high temperature. In addition, the PA third-order input intercept point and adjacent channel power ratio all decrease with stress. © 2007 IEEE

Low-Power Cmos Wireless Mems Motion Sensor For Physiological Activity Monitoring

In this paper, a short distance wireless sensor node AccuMicroMotion for physiological activity monitoring is proposed for detecting motions in six degrees of freedom. System architecture, relevant microstructures, and electronic circuits to implement the sensor node are presented. A three-axis micro-electromechanical systems (MEMS) accelerometer and a z-axis gyroscope are designed and fabricated using a new deep-reactive ion-etch CMOS-MEMS process. The interface circuits, an analog-to-digital converter, and a wireless transmitter are designed using Taiwan Semiconductor Manufacturing Company 0.35-μm CMOS process, wherein the interface circuits adopt chopper stabilization technique and can resolve a signal (dc to 1 kHz) as low as 200 nV from the microsensors; digitized outputs from the microsensors are transmitted by a 900-MHz amplitude-shift-keying radio-frequency transmitter that delivers a 2.2-mW power to a 50-Ω antenna. The system draws an average current of 4.8 mA from a 3-V supply when six sensors are in operation simultaneously and provides an overall 60-dB dynamic range. © 2005 IEEE

Analysis And Modeling Of Lc Oscillator Reliability

In this paper, MOS device degradations due to hot carrier and gate oxide breakdown are shown experimentally, and their effects on the NMOS LC oscillator have been evaluated analytically and through SpectreRF simulation. The reduction in transconductance of the differential pair transistors may cause the oscillation to cease. The amplitude of oscillation reduces as the equivalent tank resistance decreases due to the breakdown effect on the MOS varactor. The reduction of amplitude reduces the tank capacitances, and therefore shifts the frequency of oscillation and increases the oscillator phase noise. The tank amplitude of the oscillator is derived analytically. A closed-form expression for the average capacitance of the varactor that accounts for large-signal effects is presented. Finally, a set of guidelines to design an LC oscillator in reliability is presented. © 2005 IEEE

Rf Reliability Of Mosfets Subject To Electrical Stress

The impact of gate and drain voltage stress on the analog performance of MOSFETs at RF frequencies was studied systematically. 0.16-μm NMOSFETs have been evaluated experimental to examine the RF performance metrics such as cutoff frequency, linearity, noise figure, and I f noise. A methodology is presented to study the reliability in MOSFETs subject to stress. Both circuit simulation and measurement data are employed to prove the finding and methodology. © 2004 IEEE